[PDF.23kf] High Level Synthesis of ASICs under Timing and Synchronization Constraints (The Springer International Series in Engineering and Computer Science)

High Level Synthesis of ASICs under Timing and Synchronization Constraints (The Springer International Series in Engineering and Computer Science)

[PDF.cz95] High Level Synthesis of ASICs under Timing and Synchronization Constraints (The Springer International Series in Engineering and Computer Science)

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 | #5820334 in Books |  Springer |  1992-05-31 | Ingredients: Example Ingredients | Original language:English | PDF # 1 |  9.21 x.81 x6.14l,1.35 | File type: PDF | 294 pages

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Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses both theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioral level description of hardware to a synchronous logic-level implementation consis...

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