[PDF.29dr] Modeling of Electrical Overstress in Integrated Circuits (The Springer International Series in Engineering and Computer Science)

Modeling of Electrical Overstress in Integrated Circuits (The Springer International Series in Engineering and Computer Science)

[PDF.li19] Modeling of Electrical Overstress in Integrated Circuits (The Springer International Series in Engineering and Computer Science)

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 | #12849066 in Books |  Springer |  1994-11-30 | Original language:English | PDF # 1 |  9.21 x.50 x6.14l,.87 | File type: PDF | 148 pages

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Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability concerns are becoming more serious with the downward scaling of device feature sizes. Modeling of Electrical Overstress in Integrated Circuits presents a comprehensive analysis of EOS/ESD-related failures in I/O protection devices in integrated circuits.
The design of I/O protection circuits ha...

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